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| (R) TDA7330B SINGLE CHIP RDS DEMODULATOR + FILTER HIGH PERFORMANCE, 57KHz BANDPASS FILTER (8th ORDER) FILTER ADJUSTMENT FREE AND WITHOUT EXTERNAL COMPONENTS PURELY DIGITAL RDS DEMODULATION WITHOUT EXTERNAL COMPONENTS ARI (SK INDICATION) AND RDS SIGNAL QUALITY OUTPUT 4.332MHz CRYSTAL OSCILLATOR (8.664MHz OPTIONAL) LOW NOISE MIXED BIPOLAR/CMOS TECHNOLOGY DESCRIPTION The TDA7330B is a RDS demodulator. It recovers the additional inaudible RDS information which is transmitted by FM radio broadcasting stations. The output data signal (RDDA) and clock signal (RDCL) can be further processed by a suitable RDS decoder (microprocessor). The device operates in accordance with the EBU (European Broadcasting Union) specifications. The IC includes a 2nd order antialiasing input filBLOCK DIAGRAM DIP20 SO20 ORDERING NUMBERS: TDA7330B TDA7330BD ter, a 57KHz switched capacitor band pass filter, a smoothing filter and cross detector, a bit rate clock recovery circuit, a 57KHz PLL, BI-PHASE PSK decoder, differential decoding circuit, ARI indication and RDS signal quality output. November 1999 1/9 TDA7330B ABSOLUTE MAXIMUM RATINGS Symbol VCC Top Tstg Supply Voltage Operating Temperature Range Storage Temperature Parameter Value 7 -40 to 85 -40 to 150 Unit V C C THERMAL DATA Symbol Rth j-case Description Thermal Resistance Junction-case Typ. DIP20 100 SO20 200 Unit C/W PIN CONNECTION (Top view) PIN FUNCTION Nr. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Name MUXIN Vref COMP FIL OUT GND T1 T3 T4 OSC OUT OSC IN T57 RDCL RDDA QUAL ARI Description RDS input signal. Reference voltage Not inverting comparator input (smoothing filter) Filter Output Ground Testing output pin (not to be used) Testing output pin (not to be used) Testing output pin (not to be used) Oscillator output Oscillator Input Testing output pin: 57KHz clock output RDS clock output (1187.5Hz) RDS data output Output for signal quality indication (High = good) Output for ARI indication (High when RDS + ARI signals are present) (High when only ARI is present) (Low when only RDS is present) (indefined when no signal is present) Supply Voltage Testing output pin (not to be used) Frequency selector pin: open = 4.332MHz, closed to VCC = 8.664MHz Test mode pin (open = normal RUN) (closed to VCC = Test mode) Reset Input for testing (active high) 16 17 18 19 20 2/9 VCC T2 FSEL TM POR TDA7330B ELECTRICAL CHARACTERISTICS (VCC = 5V, Tamb = 25C; Rg = 600; fosc = 4.332MHz; VIN = 20mVrms unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit SUPPLY VCC IS RPOR PORON Supply Voltage Supply Current POR Pull Down Resistor POR Threshold 4.5 pin 20 5 9 40 2.5 5.5 V mA K V FILTER(measured an pin 4 FILOUT) FC BW G A Ph Center Frequency 3dB Bandwidth Gain Attenuation 56.5 2.5 18 18 50 35 57 3 20 22 80 50 0.5 1 2 160 40 57.5 3.5 22 KHz KHz dB dB dB dB DEG DEG DEG K dB Vrms mVrms K Phase non linearity f = 57KHz f = +4KHz f = 38KHz; Vi = 500mVrms f = 67KHz; Vi = 250mVrms A (see note1) B (see note1) C (see note1) Vi = 3mVrms f = 19KHz; T3 < -40dB (see note2) f = 57KHz (RDS + ARI) Pin 4 Ri S/N Vi RL Input Impedance Signal to Noise Ratio Maximum Input Signal Capability Load Impedance 100 30 5 7.5 10 200 1 50 100 CROSS DETECTOR RA Resistance pin 3-4 15 21 28 K OSCILLATOR FOSC VCLL VCLH Oscillator Frequency Clock Input level LOW (pin 10) Clock Input Level HIGH (pin 10) Output Amplitude (pin 9) FSEL = Open (*) FSEL = Closed to VCC (**) 4 4.5 4.332 8.664 1 MHz MHz V V VPP (*) FSEL pin has an internal 40K pull down resistor A 4.332MHz QUARTZ must be used (**) A 8.664MHz QUARTZ must be used. DEMODULATOR fO SRDS SARI Tlock VOH VOL fRDS tD Max Oscillator Deviation RDS Detection Sensitivity ARI Detection Sensitivity RDS Lockup Time Output HIGH Voltage Output LOW Voltage Data Rate for RDS RDDA Transition versus RDCL FSEL = Open 1 3 100 IL = 0.5mA; pins 12, 13, 14, 15 IL = 0.5mA; pins 12, 13, 14, 15 RDCL pin (see figure 2) 4 1 1187.5 4.3 + 1.2 KHz mVrms mVrms ms V V Hz sec Note(1): The phase non linearity is defined as: Ph = | -2 f2 + f1 + f3 | where fx is the input-output phase difference at the frequency fx (x = 1,2,3) 3/9 TDA7330B ELECTRICAL CHARACTERISTICS (continued) Measure A B C f1 (KHz) 56.5 56 55.5 f2 (KHz) 57 57 57 f3 (KHz) 57.5 58 58.5 Ph max <5 <7.5 <10 Note(2): The 3th harmonic (57KHz) must be less than -40dB in respect to the input signal 19KHz plus gain. Figure 2: RDS timing diagram OUTPUT TIMING The generated 1187.5Hz output clock (RDCL line) is synchronized to the incoming data. According to the internal PLL lock condition this Figure 3: Test Circuit data change can results on the falling or on the rising clock edge. Whichever clock edge is used by the decoder (rising or falling edge) the data will remain valid for 416.7 sec after the clock transition. 4/9 TDA7330B APPLICATION SUGGESTION A good DC decoupling between VCC and GROUND is necessary: a 100nF ceramic capacitor, with low resistance and low inductance at high frequency, directly connected on pin 16 (VCC)and 5 (GND) is recommended. A small series inductance (100H) or resistor (27) may be used for supply line filtering. The Layout path pin2 - C2 - pin5 must be as short as possible. If the supply line, after the power on has a soft and disturbed (spikes) slope, a capacitor of 100nF, between POR and VCC, is racommended. The various testing pins have no sense for the customer. Figure 4: P.C. board and component layout of fig. 3 (1:1 scale) 5/9 TDA7330B Figure 5: Gain vs. Frequency Figure 6: Group Delay vs. Frequency 6/9 TDA7330B DIM. MIN. a1 B b b1 D E e e3 F I L Z 0.254 1.39 mm TYP. MAX. MIN. 0.010 1.65 0.45 0.25 25.4 8.5 2.54 22.86 7.1 3.93 3.3 1.34 0.055 inch TYP. MAX. OUTLINE AND MECHANICAL DATA 0.065 0.018 0.010 1.000 0.335 0.100 0.900 0.280 0.155 0.130 DIP20 0.053 7/9 TDA7330B mm DIM. MIN. A A1 B C D E e H h L K 10 0.25 0.4 2.35 0.1 0.33 0.23 12.6 7.4 1.27 10.65 0.75 1.27 0.394 0.010 0.016 TYP. MAX. 2.65 0.3 0.51 0.32 13 7.6 MIN. 0.093 0.004 0.013 0.009 0.496 0.291 0.050 0.419 0.030 0.050 TYP. MAX. 0.104 0.012 0.020 0.013 0.512 0.299 inch OUTLINE AND MECHANICAL DATA SO20 0 (min.)8 (max.) L h x 45 A B e K H D A1 C 20 11 E 1 0 1 SO20MEC 8/9 TDA7330B Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 9/9 |
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